1. Field of the Invention
This invention relates generally to minicomputing systems and more particularly to the test and verification of storage hierarchies having a high speed, low capacity storage device coupled to lower speed high capacity storage devices.
2. Description of the Prior Art
Data processing systems frequently have a high speed buffer memory or cache store between a central processor unit (CPU) and a main memory. The CPU in normal operation requests information from the cache. If the information is not stored in cache, then the information is requested of main memory. The system objective is to have a high percentage of information requested by the CPU found in the high speed cache rather than in the slower speed main memory. This results in improved overall system performance.
Since the cache is normally invisible to the software during normal operation many malfunctions in the cache will not show up as system faults since the information is retrieved from main memory if cache doesn't respond to the CPU request. The system will therefore not operate at its throughput.
Prior art systems use software diagnostics to check out the cache. These diagnostics under CPU control write known data into cache, then read the cache with the CPU verifying the data. Unfortunately cache malfunctions result in the information being read from main memory. To overcome this more elaborate diagnostics are written to transfer information from main memory to cache, turn cache off and rewrite that section of main memory with different information, then read cache and compare it against the original information from main memory. The disadvantages of the elaborate software diagnostic procedures are overcome by the apparatus of this invention.